TRANSPARENT: A System for RTL Testability Analysis, DFT Guidance and Hierarchical Test Generation

We discuss a methodology for analyzing the testability of large hierarchical RTL designs, based upon the existence of module reachability paths, suitable for automatically deriving globally applicable test from locally generated vectors. Such reachability paths utilize module transparency behavior, as captured by the introduced channel transparency definition. Lack of transparency and unreachable module I/Os pinpoint testability bottlenecks apt for efficient DFT modifications. Application of this methodology on example designs results in significant fault coverage improvement and test generation speedup, as compared to complete design gate-level ATPG. Introduction Continuous improvements in silicon manufacturing technology have enabled the realization of extremely large and complex designs that have by far outpaced the capacity of the EDA tools to handle them as monolithic entities. Significant effort has been consequently invested in devising hierarchical approaches, either top/down or bottom/up, for accommodating current and future design and test needs. The hierarchical test generation concept, depicted in Fig. 1, has been long ago proposed as a promising and viable alternative to the slow and complex global design test generation process (1-5). Local test can be quickly and efficiently generated for each module of a hierarchical design and consequently translated to global test, applicable at the complete design boundary. Although such approaches are independent of the local test generation mechanism, the actual test vectors and the targeted fault models, their success has been heavily dependent on the efficacy of the test translation process. Test translation approaches that reason exhaustively on the functional space of the upstream vector justification and downstream response propagation logic, such as in (1, 4, 6, 7), are doomed by complexity, despite being complete. DFT modifications can alleviate this problem by providing alternative reachability paths, however they are expensive and need to be incorporated judiciously. Test transparency related behavior has been alternatively employed for the surrounding modules, while translating local into global test (3, 8-10). Although such approaches make test translation a fast and trivial process when transparency exists, partial transparency or lack of transparency, even for a single module, proves catastrophic for the test translation process. In order to preserve high fault coverage, an efficient mechanism for defining modular transparency and guiding DFT modifications to address the lack of such transparency is necessitated. In the following sections, we introduce TRANSPARENT, a system for RTL testability analysis, DFT guidance and hierarchical test generation, based on the concept of transparency channels. We first provide an overview of the system, followed by a detailed discussion of its constituent parts. We present the channel transparency definition and its application on module reachability analysis and we discuss testability bottleneck identification and minimization, along with its potential for guiding DFT modifications. We then derive a hierarchical test generation scheme, wherein reachability paths are utilized for translating local module vectors into complete design test. Finally, we demonstrate the proposed methodology on example hierarchical designs and we report our results in comparison to complete circuit ATPG. FIGURE 1: HIERARCHICAL TEST GENERATION, TEST TRANSLATION AND DFT APPROACHES – BENEFITS & DRAWBACKS C o m p l e t e D e s i g n P r i m a r y O u t p u t s P r i m a r y I n p u t s • S l o w • C o m p l e x • F a s t • E f f i c i e n t • S l o w • C o m p l e t e • F a s t • I n c o m p l e t e M o d u l e U n d e r T e s t U p s t r e a m V e c t o r J u s t i f i c a t i o n L o g i c D o w n s t r e a m R e s p o n s e P r o p a g a t i o n L o g i c C o m p l e t e D e s i g n T e s t G e n e r a t i o n L o c a l M o d u l e T e s t G e n e r a t i o n L o c a l t o G l o b a l T e s t T r a n s l a t i o n U s i n g C o m p l e t e F u n c t i o n a l S p a c e L o c a l t o G l o b a l T e s t T r a n s l a t i o n U s i n g o n l y T r a n s p a r e n c y B e h a v i o r • E f f i c i e n t • E x p e n s i v e D F T M o d i f i c a t io n s f o r M o d u l e R e a c h a b i l i t y D F T D F T Upstrea Vector Just ficat n Logic Do nstream R sponse Pr agation ogic FIGURE 2: TRANSPARENT – SYSTEM OVERVIEW System Overview The system TRANSPARENT, described herein, comprises a methodology for analyzing the testability of RTL hierarchical design, reporting testability bottlenecks for guiding efficient DFT modifications and generating test in a hierarchical fashion. It provides early in the design cycle a hierarchical testability assessment, based on modular transparency, without exhaustively reasoning on the complete design functional space, in order to avoid complexity issues. The analysis is symbolic and therefore independent of the actual test vectors, the test generation mechanism and the underlying fault model. Furthermore, it handles variable bitwidth and sub-word signal entities and addresses both data and control path modules, combinational and sequential. The proposed system is significantly faster than full circuit, gate-level ATPG, while providing very high fault coverage through few, yet effective DFT modifications. An overview of the TRANSPARENT system is depicted in Fig. 2. Starting with the hierarchical RTL design description, local test vectors and responses are generated for each module. Subsequently, a design traversal algorithm examines the reachability of each module in the design and identifies test translation paths, based on the notion of transparency channels that is introduced in the following section. The traversal algorithm provides the reachability paths and test translation templates on the original design, based on which the local test is translated into global design test. It further reports the identified testability bottlenecks in the design and a set of alternative reachability paths and test translation templates, valid on a modified design wherein the bottlenecks are resolved. These templates are used for obtaining global test from local vectors on the modified for testability design. The constituent parts of the system are further discussed in the following sections. Testability Analysis In this section we describe the testability analysis phase of the TRANSPARENT system. We define the transparency channel notion and we provide the design traversal algorithm that examines reachability paths for each module and reports test translation templates and potential testability bottlenecks. A. Transparency Channels The transparency channel definition, introduced in this section, alleviates the complexity of examining the complete functional space of each module during test translation. It constitutes, thus, a search space pruning mechanism that facilitates an efficient trade-off between completeness and complexity of the test translation process. The underlying theme for distinguishing test translation related behavior is the requirement for bulk mode, instead of case-by-case, test justification and propagation, while utilizing only existing module functionality. In this sense, channels provide a pessimistic view of a module’s functional space. Channels attempt to capture bulk mode, test translation related behavior of modules, in terms of bijection functions between input and output signal entities. Channels are instantiated upon the compliance of a number of conditions that require a specific potential on signal entities. The required potential may be either controllability or observability of the signal entity to a set comprising all possible values, a known constant value, an unknown but constant value, mutually exclusive values, or same values on the bits of the signal entity. Channels incorporate time considerations and may be defined either between an input signal entity and an output signal entity or between two output signal entities, in order to account for statedependent, sequential logic behavior. Signal entities may be defined either on the full word bitwidth or on sub-word bitwidths. In order to be able to support and combine variable bitwidth channels on a search path, the notions of well and drain are employed. Wells are either primary inputs or internal modules with controllability potential on signal entities. Similarly, drains are either primary outputs, or internal modules with observability potential on signal entities. A succinct definition of the transparency channels is given in Fig. 3, along with a few examples of simple modules and associated channels. In summary, channels capture test translation behavior of data and control path, combinational and sequential modules, variable bitwidths and sub-word signal entities. An extensive description of the channels is given in (10). Hierarchical RTL Design Description Modular Local Test Generation Transparency Channels for Modules Design Traversal Algorithm for Reachability Analysis & Test Translation Path Identification Local Test Vectors & Responses Translation Paths & Templates on Original Design Testability Bottlenecks Test Translation on Original Design Test Translation on Modified Design Translation Paths & Templates on Modified Design Bottleneck Resolution through DFT Modifications Global Test on Original Design Global Test on Modified Design